Eecient Barriers for Distributed Shared Memory Computers University of Colorado at Boulder Eecient Barriers for Distributed Shared Memory Computers

Barrier algorithms are central to the performance of numerous algorithms on scalable, high-performance architectures. Numerous barrier algorithms have been suggested and studied for Non-Uniform Memory Access (NUMA) architectures, but less work has been done for Cache Only Memory Access (COMA) or attraction memory 2] architectures such as the KSR-1. In this paper, we present two new barrier algorithms that ooer the best performance we have recorded on the KSR-1 distributed cache multiprocessor. We discuss the trade-oos and the performance of seven algorithms on two architectures. The new barrier algorithms adapt well to a hierarchical caching memory model and take advantage of parallel communication ooered by most multiprocessor interconnection networks. Performance results are shown for a 256-processor KSR-1 and a 20-processor Sequent Symmetry.